WM8146

Product Preview

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

12

OPERATING MODE TIMING DIAGRAMS

The following diagrams output data, MCLK, VSMP and input video requirements for operation of the

most commonly used modes as shown in Table 1 . The diagrams are identical for both CDS and

non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X

denotes invalid data.

INPUT

VIDEO

MCLK

VSMP

OP[7:0]

16.5 MCLK PERIODS

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

R

A

R

B

G

A

G

B

B

A

B

B

G

A

G

B

B

A

B

B

Figure 11 Mode 1 Operation

16.5 MCLK PERIODS

X

MCLK

VSMP

INPUT VIDEO

OP[7:0]

R

A

R

B

X

X

X

R

A

R

B

X

X

X

X

R

A

R

B

X

X

X

X

R

A

R

B

X

X

X

X

R

A

R

B

Figure 12 Mode 2 Operation

MCLK

VSMP

OP[7:0]

INPUT VIDEO

23.5 MCLK PERIODS

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

R

A

R

B

Figure 13 Mode 3 Operation