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WM8146

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

9

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is amplified by a 5-bit PGA then added

to the output of an 8-bit (+sign) offset DAC to compensate for sensor d.c. offsets. The gain and offset

for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[4:0].

The following diagram shows the signal path through the device.

V

RESET

V

MID

V

3

CDS = 1

CDS = 0

(1-2*DSIGN)*(DAC[7:0]/255)*(V

analo g

-

D

1

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

D

2

CDS, DAC[7:0], DSIGN, DACRNG, PGA[4:0]

and INVOP are set by programming internal

control registers.

CDS=1 for CDS, 0 for non-CDS

V

V

V

V

IN

V

PGA gain

A = 0.5+(PGA[4:0]*0.25)

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 =4095-D1 if INVOP = 1

Offset

DAC

+

V

2

V

1

+

+

X

TO MULTIPLEXER

FOR 8-BIT OUTPUT

Figure 8 Signal Flow Diagram

The following equations enable the user to calculate the settings required for the PGAs and offset

DACs.

INPUT SAMPLING AND REFERENCING

(i.e. CDS operation).

GAIN ADJUST

The signal is then multiplied by the PGA gain, approximately 0.5 to 8.25 in 32 equal gain steps.

OFFSET (BLACK-LEVEL) ADJUST

The resultant signal is added to the Offset DAC output which has a range of VMID/2 (or 1.5*VMID/2 if

the DACRNG bit is set).

ANALOGUE TO DIGITAL CONVERSION

The analogue signal is then converted to a 12-bit unsigned number. This is equivalent to a

-2047 and +2048. If the input is over-range, it will be clipped to within the range (-2047,2048).

2047 is added to the ADC output, to give code 2047 for zero input signal to the ADC.

This is

equivalent to the +VMID shown in the block diagram on page 1.