WM8144 datasheet(21/27 Pages) WOLFSON

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WM8144-10

Wolfson Microelectronics

Figure 16: Serial Interface Timing

Figure 17: Parallel Interface Timing

Configuration of the WM8144-10

The WM8144-10 can be configured through a serial

interface or a parallel interface. Selection of the

interface type is by the PNS pin which must be tied

high (parallel) or low (serial).

Serial Interface

The serial interface consists of three pins (refer to

figure 16 ). A six-bit address is clocked in MSB first

followed by an eight-bit data word, also MSB first.

Each bit is latched on the rising edge of SCK, which

can operate at upto 12MHz. Once the data has been

shifted into the device, a pulse is applied to SEN to

transfer the data to the appropriate internal register.

Parallel Interface

The parallel interface uses bits [9:2] of the OP bus as

well as the STB, DNA and RNW pins (refer to figure

17). Pin RNW must be low during a write operation.

The DNA pin defines whether the data byte is address

(low) or data (high). The data bus OP[9:2] is latched in

during the low period of STB. This interface is

compatible with the Extended Parallel Port interface.

Internal Register Definition

Table 5 summarises the internal register content. The

first 4 addresses in the table are used to program setup

registers and to provide a software reset feature ( 00H

is reserved ). The remaining 7 entries in the table define

Table 6: Register Map Contents

the address location of internal data registers. In each case,

a further three sub-addresses are defined for the red, green

and blue register. Selection between the red, green and

blue registers is performed by address bits a1 and a0, as

defined in the table. Setting both a1 and a0 equal to 1 forces

all three registers to be updated to the same data value.

Blank entries can be taken as 'don't care' values.

Address

Description

Def'lt

Bit

<a5:a0>

(Hex)

000000 Reserved

000001 Setup Register 1

DVMODE

VSMP6M

DEFDV

DEFPO

DEFPG

MONO

CDS

ENADC

000010 Setup Register 2

CDATOUT

BYPASS

LATCHOP

INVOP

MUXOP

000011 Setup Register 3

CHAN[1]

CHAN[0]

CDSREF[1] CDSREF[0]

PWP[1]

PWP[0]

RLC[1]

RLC[0]

000100 Software Reset

000101 Setup Register 4

DACRNG

1000xx DAC values

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

1001xx DAC signs

DSIGN

1010xx PGA Gains

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

1011xx Pixel Offsets

OFF[5]

OFF[4]

OFF[3]

OFF[2]

OFF[1]

OFF[0]

1100xx Pixel Gain MSB

GAIN[11]

GAIN[10]

GAIN[9]

GAIN[8]

GAIN[7]

GAIN[6]

GAIN[5]

GAIN[4]

1101xx Pixel Gain LSB

GAIN[3]

GAIN[2]

GAIN[1]

GAIN[0]

1110xx Data Valid

Address LSB decode

Red Register

Green Register

Blue Register

Red, Green and Blue

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