WM8144 datasheet(13/27 Pages) WOLFSON

13 / 27 page

WM8144-10

Wolfson Microelectronics

Digital Signal Processing

By default, the output from the ADC passes through the

digital compensation block without being altered and is

output directly on the OP[9:0] pins. If required, the pixel

data from the ADC can be processed further by the dig-

ital compensation block (Figure 8). This section describes

the sub-blocks of the digital compensation block.

CDATA Demultiplexor

The input to this block is coefficient data presented to the

CDATA[7:0] pins at twice the pixel rate. i.e. two eight-bit

words are input for each pixel of video data.

Data Partitioning

The sixteen bits of data per pixel from the CDATA

Demultiplexor is partitioned into pixel offset, pixel gain

and pixel valid bits (Table 3) . Table 4 details the resulting

range and resolution options.

Pixel Offset Adder

This uses the offset coefficients that are either supplied

externally via the CDATA interface or from the internal

default registers. The object of this block is to correct for

the small offsets which can occur from the CCD on a

pixel-by-pixel basis. The output from the Pixel Offset

Adder is limited to be between 0 and 1023(dec).

Pixel Gain Adjust

This block corrects for the pixel-by-pixel shading curve

non-uniformity and photo response non-uniformity within

the CCD sensor. This block has a gain range of 0 to 2.

The output word from the Pixel Gain Adjust is limited to

between 0 and 1023(dec).

Effect of digital compensation on ADC output

The combined effect of the digital compensation sec-

tions on the ADC output is summarised by the formula:

OP[9:0] = (ADCOP + POC) * PSCF

where:

All values are decimal

OP[9:0] is the 10 bit result output from the WM8144-10

ADCOP is a 10 bit unsigned number from the ADC

POC is a 2's compliment number divided byNUMBER OF

POC BITS ALLOCATED/2

PSCF is an unsigned number divided by NUMBER OF

PSC BITS ALLOCATED/2

For this example assume PSC is allocated 12 bits and

POC

allocated

bits

(refer

table

3:DVMODE,PWP0,PWP1 = 0). Table 1 shows some ex-

amples of the effect of the digital backend on the ADC

output.

ADCOP

POC

PSC

OP[9:0]

ORNG

Range

0:1023

-8:7

0:4095

0:1023

0:1

Default

2048 (x1)

Ex 1

512

2048

512

Ex 2

512

-7

2048

505

Ex 3

512

2048

518

Ex 4

1022

2048

1023

Ex 5

1022

512

257

Ex 6

512

2560

640

Ex 7

512

128

Ex 8

512

4095

1023

Ex 9

511

4095

1021

Table 2: Examples of digital backend calculation

Theory of Operation (contd.)

PIXEL OFFSET

ADDER

LIMIT

MUX

DEFAULT

MUX

PIXEL GAIN

ADJUST

LIMIT

DATA VALID

GENERATION

DATA

PARTITIONING

DEMUX

AND MUX

DATA

LATCH

OUT OF RANGE

GENERATION

4,5 or 6

612

12,11 or 10

ADC

ORNG INPUT TO

8/10 MUX BLOCK

OP[9:0] INPUT TO

8/10 MUX BLOCK

DV OUTPUT

ADCOP

CDATA

DEFAULT

Figure 12

Figure 8

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