Wolfson Microelectronics

12

WM5628L, WM5628

Serial Input DAC Address and Output Tables

Using these inputs individual DACs can be updated using

one 12 bit serial input word and the LOAD pin. Using both

LOAD and LDAC, all or selected DACs can be updated

after an appropriate number of data words have been

inputted. Figures 3 &4 illustrate operation with the 8 clock

pulses available from some microprocessors. If the data

input is interrupted in this way the clock input must be held

low during the break in clock pulses.

The RNG bit controls the DAC output range. When RNG = 0

the output is between Vref(A,B,C,D) and GND and when

RNG = 1 the range is between 2 x Vref (A,B,C,D) and GND.

A2

A1

A0

DAC Updated

0

0

0

DACA

0

0

1

DACB

0

1

0

DACC

0

1

1

DACD

1

0

0

DACE

1

0

1

DACF

1

1

0

DACG

1

1

1

DACH

D7

D6

D5

D4

D3

D2

D1

D0

Output Voltage

0

0

0

0

0

0

0

0

GND

0

0

0

0

0

0

0

1

(1/256) x Ref (1 + RNG)

0

1

1

1

1

1

1

1

(127/256) x Ref (1 + RNG)

1

0

0

0

0

0

0

0

(128/256) x Ref (1 + RNG)

1

1

1

1

1

1

1

1

(255/256) x Ref (1 + RNG)