2001-03-05

Page 1

MDST-0009-00

Vaishali Semiconductor

1300 White Oaks Road, Ste. 200

Campbell

CA 95008

Ph. 408.377.6060

Fax 408.377.6063

Applications

•= Oscillator Replacement

•= LCD monitor clock source

General Description

The VT98501 is a 3.3V CMOS, clock multiplier integrated circuit. The device provides an excellent quality

high frequency output clock from a lower frequency crystal or clock input. Tri-level selection inputs S0 and

S1 are used to select any one of nine multipliers, stored in the on-board ROM, and apply it to the input to

produce the desired output. The resulting output includes many commonly used frequencies up to 160

MHz. Phase Locked Loop (PLL) technology allows the device to use an input signal from an inexpensive

crystal.

When Output Enable (OE) is low, the clock output is in high impedance state.

The VT98501, when used with an inexpensive crystal, provides a cost-effective clock source for most

electronic systems.

Figure 1. Functional Block Diagram

Advance Information

VT98501

Low Phase Noise Clock Multiplier

Features

•= Low phase noise

•= Zero ppm multiplication error

•= Input clock frequency 2 - 50 MHz.

•= Input crystal frequency 5 – 27 MHz

•= Output clock frequencies up to 160 MHz.

•= 5V tolerant inputs and output

•= Exceptionally low jitter: 25 ps one sigma

•= Fully Compatible with all popular CPUs

•= Duty Cycle of 45/55 up to 160 MHz.

•= 25mA drive capability at TTL levels

•= High-Z output for board level testing

X1/ICLK

VDD

S0

S1

Output Enable

Clock or

Xtal

input

PLL

Clock

Multiplier

&

ROM

Output

Buffer

Xtal.

Osc.

GND

X2

Optional

caps

CLK

Advance Information

VT98501

3.3V Low Phase Noise Clock Multiplier

Figure 2. Pin Assignment

1

2

3

4

8

7

6

5

X1/ICLK

VDD

GND

S1

X2

OE

S0

CLK

8-pin SOIC