Features
• Packaged in 16-pin SOIC (Pb free)
• Uses fundamental 10 - 27 MHz crystal or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 170 MHz at 3.3 V
• Output Enable function tri-states outptus
• Low phase noise: -132 dBc/Hz at 10 kHz
• Low jitter - 18 ps one sigma
• Full swing CMOS outputs with 25 mA drive capability at
TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature range (-40 to +85°C)
• 3.3 V or 5 V core VDD. Output clock can operate down to 2.5 V