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H5GQ1H24AFR-R0C датащи(PDF) 173 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C датащи(HTML) 173 Page - Hynix Semiconductor |
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173 / 173 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 173 H5GQ1H24AFR Figure. 92 Internal Block Diagram DQ2 Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D DQ1 DQ3 WCK01# SSH, Scan Shift Pin RESET# SCK, Scan Clock Pin CS# SOUT, Scan Out Pin EDC0 SEN, Scan Enable Pin SEN SOE#, Scan Output Enable Pin MF Pins under test Dedicated Scan D FF per signal under test Signals in scan chain: DQ[31:0], EDC[3:1], DBI#[3:0], WCK01, WCK01#, WCK23, WCK23#, RAS#, CAS#, WE#, CKE#, ABI#, A[7:0]***, CK, CK#, ZQ Note: A[7:0]*** are multiplexed pins and represent A[12:8] and BA[3:0] Signals not in the scan chain: VDDQ, VSSQ, VDD, VSS, VREFx |
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