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Reference Path ’R’ Divider

the referenced path features a 14-bit divider (rfp_div_ratio, Reg03h<13:0> table 14) and can divide input signals

at up to 200 Mhz by numbers from 1 to 16,383. the selected input reference source may be divided or bypassed

(rfp_div_select), and applied to the phase detector reference input.

VCO Auto Tuning and Serial Port Clocks

the optional Vco auto tuning state machine and the Vco serial Port clocks use the undivided selected external

reference signal, as determined by rfp_xref_sin_select Reg12h<6> (table 29), and as shown in figure 10.

Reference Path Test Features

a fractional synthesizer is a complex combination of a low phase noise analog oscillator running in close proximity with

a nearly randomly modulated delta-sigma digital modulator.

clean spur free operation of the synthesizer requires proper board layout of power and grounds. spurious sources

are often difficult to identify and may be related to harmonics of the digital modulation which land near the operating

frequency of the Vco, or they may arise from repeating patterns in the digital modulation itself . the loop filter and the

fractional modulator are designed to suppress these fractional spurs, but it is sometimes the case that the isolation

of the spurious products comes from layout issues. the problem is how to identify the sources of spurious products

if they occur?

the reference path of the hMc701LP6ce features some interesting test options for clocking the digital portion of the

synthesizer which may provide for a better understanding of the source of reference spurs should they occur. see

figure 10, table 12 and table 29 for more register details.

it is possible for example to set the synthesizer to integer mode of operation, where the digital harmonics normally

fall directly on the Vco frequency. We might chose for example to use the sine source (rfp_buf_sine_sel=1, div_

todig_en=0) to drive the reference divider. in such a case the delta sigma modulator is not normally used, however if

(sqr_todig_en=1 and dsm_xref_sin_select=0). this would allow the square wave clock to be set independently of

the locked integer mode Vco, and hence measure the coupling of the digital to the sidebands of the Vco at various

frequencies. such a test can help in identifying and debugging grounding and layout issues in the application circuit

related to the digital portion of the PcB should they occur. in general it is recommended to follow the suggested layout

closely to avoid any such problems.

Figure 10. Reference Path Block Diagram

HMC701LP6CE

v05.0110

8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER