P89LPC9151FDH datasheet(63/91 Pages) NXP

номер детали	P89LPC9151FDH

подробное описание детали	8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC

PDF	91 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

63 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

criteria, the boundary limits will again be compared after all 8 bits have been converted.

The boundary status register (BNDSTA0) flags the channels which caused a boundary

interrupt.

8.7 DAC output to a port pin with high output impedance

The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is

used to hold the value fed to the DAC. After a value has been written to the DAC (written

to AD1DAT3), the DAC output will appear on the channel 3 pin.

8.8 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.9 Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause the

device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.

In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is

enabled, it will consume power. Power can be reduced by disabling the A/D.

P89LPC9151FDH датащи(PDF) 63 Page - NXP Semiconductors