P89LPC9151FDH datasheet(39/91 Pages) NXP

39 / 91 page

P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

39 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5)

and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD

has reached its specified level.

7.6 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to

±5 % at room temperature. This oscillator can be used to save power when a high clock

frequency is not needed.

7.7 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P0.5/CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When the frequency above

12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in

reset at power-up until VDD has reached its specified level.

Remark: When using P0.5 as a clock input option, please make sure that P0.5 is

configured as input only mode.

7.8 Clock sources switch on the fly

P89LPC9151/9161/9171 can implement clock source switch in any sources of watchdog

oscillator, 7 MHz/14 MHz IRC oscillator, or external clock input during code is running.

CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is

cleared when starting clock source switch and set when completed. Notice that when

CLKOK is ‘0’, writing to CLKCON register is not allowed.

Fig 10. Block diagram of oscillator control

÷2

002aae574

RTC

CPU

WDT

DIVM

CCLK

OSCCLK

XCLK

RCCLK

I2C-BUS

UART

PCLK

TIMER 0 AND

TIMER 1

CLKIN

OSCILLATOR

WATCHDOG

OSCILLATOR

PCLK

RCCLK

SPI

(P89LPC9161)

RTCS1:0

ADC1/DAC1

CLKOUT

(7.3728 MHz/14.7456 MHz

± 1 %)

(400 kHz

± 5 %)

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