DS1876 datasheet(19/69 Pages) MAXIM

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______________________________________________________________________________________ 19

SFP Controller with Dual LDD Interface

Transmit Fault (TXFOUT) Output

TXFOUT can be triggered by all alarms, warnings, QTs,

TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six

ADC alarms and warnings are controlled by enable bits

(Table 01h/05h, Registers F8h and FCh). See Figures

11a and 11b for nonlatched and latched operation for

TXFOUT. The CNFGB register (Table 02h, Register 89h)

controls the latching of the alarms.

Die Identification

The DS1876 has an ID hardcoded in its memory. Two

registers (Table 02h, Registers 86h

-87h) are assigned

for this feature. Register 86h reads 76h to identify the

part as the DS1876; Register 87h reads the present

device version.

I2C Communication

I2C Definitions

The following terminology is commonly used to describe

I2C data transfers.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses and START and STOP conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states.

START Condition: A START condition is generated

by the master to initiate a new data transfer with a

slave. Transitioning SDA from high to low while SCL

remains high generates a START condition. See

Figure 12 for applicable timing.

STOP Condition: A STOP condition is generated

by the master to end a data transfer with a slave.

Transitioning SDA from low to high while SCL remains

high generates a STOP condition. See Figure 12 for

applicable timing.

Repeated START Condition: The master can use

a repeated START condition at the end of one data

transfer to indicate that it will immediately initiate a

new data transfer following the current one. Repeated

STARTs are commonly used during read operations

to identify a specific memory address to begin a data

transfer. A repeated START condition is issued identi-

cally to a normal START condition. See Figure 12 for

applicable timing.

Bit Write: Transitions of SDA must occur during the

low state of SCL. The data on SDA must remain valid

and unchanged during the entire high pulse of SCL

plus the setup and hold time requirements (Figure 12).

Data is shifted into the device during the rising edge

of the SCL.

Bit Read: At the end of a write operation, the master

must release the SDA bus line for the proper amount

of setup time (Figure 12) before the next rising edge

Figure 11a. TXFOUT Nonlatched Operation

Figure 11b. TXFOUT Latched Operation

DETECTION OF TXFOUT FAULT

TXFOUT

DETECTION OF TXFOUT FAULT

TXD_ OR TXFOUT RESET

TXFOUT

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