4-/6-/8-Channel, 16-Bit,

Simultaneous-Sampling ADCs

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13

Transfer Functions

Figures 8 and 9 show the transfer functions for all the

formats and devices. Code transitions occur halfway

between successive-integer LSB values.

Layout, Grounding, and Bypassing

For best performance, use PCBs with ground planes.

Ensure that digital and analog signal lines are separated

from each other. Do not run analog and digital lines paral-

lel to one another (especially clock lines), and avoid run-

ning digital lines underneath the ADC package. A single

solid GND plane configuration with digital signals routed

from one direction and analog signals from the other pro-

vides the best performance. Connect DGND, AGND, and

AGNDS pins on the MAX11047/MAX11048/MAX11049 to

this ground plane. Keep the ground return to the power

supply for this ground low impedance and as short as

possible for noise-free operation.

To achieve the highest performance, connect all the

RDC outputs to a local RDC plane on the PCB. Bypass

the RDC outputs with a total of at least 80μF of capaci-

tance. For example, if two capacitors are used, place

two 47μF, 10V X5R capacitors in 1210 case size as

close as possible to pins 22 and 49. Alternatively, if four

capacitors are used, place four 22μF, 10V X5R capaci-

tors in 1210 case size as close as possible to pins 22,

28, 43, and 49. Ensure that each capacitor is connect-

ed directly into the GND plane with an independent via.

In cases where Y5U or Z5U ceramics are used, select

higher voltage rating capacitors to compensate for the

high-voltage coefficient of these ceramic capacitors,

thus ensuring that at least 80μF of capacitance is on

the RDC plane when the plane is driven to 4.096V by

the internal reference buffer. For example, at 4.096V, a

22μF X5R ceramic capacitor with a 10V rating diminish-

es to only 20μF, whereas the same capacitor in Y5U

ceramic at 4.096V decreases to about 13μF. However,

a 22μF Y5U ceramic capacitor with a 25V rating capac-

itor is approximately 20μF at 4.096V.

Bypass AVDD and DVDD to the ground plane with

0.1μF ceramic chip capacitors on each pin as close as

possible to the device to minimize parasitic inductance.

Add at least one bulk 10μF decoupling capacitor to

AVDD and DVDD per PCB. Interconnect all of the

AVDD inputs and DVDD inputs using two solid power

planes. For best performance, bring the AVDD power

plane in on the analog interface side of the MAX11047/

MAX11048/MAX11049 and the DVDD power plane from

the digital interface side of the device.

For sampling periods near minimum (1μs) use a 1nF

C0G ceramic chip capacitor between each of the chan-

nel inputs to the ground plane as close as possible to the

MAX11047/MAX11048/MAX11049. This capacitor

reduces the inductance seen by the sampling circuitry

and reduces the voltage transient seen by the input

source circuit.

RD

(USER SUPPLIED)

CS

(USER SUPPLIED)

D0–D15

Figure 5. Readout Timing Requirements

CONFIGURATION

REGISTER

WR

(USER SUPPLIED)

CS

(USER SUPPLIED)

D0–D15

(USER SUPPLIED)

Figure 4. Programming Configuration-Register Timing

Requirements