4-/6-/8-Channel, 16-Bit,

Simultaneous-Sampling ADCs

______________________________________________________________________________________

11

source produces during a fault condition.

Figures 2 and 3 illustrate the clamp circuit voltage-cur-

1280

Ω. While the input voltage is within the range of

input clamps. Once the input voltage goes beyond this

voltage range, the clamps turn on and limit the voltage

at the input pin.

Applications Information

Digital Interface

The bidirectional, parallel, digital interface, DB0–DB3,

sets the 4-bit configuration register. This interface

configures the following control signals: chip select

(

CS), read (RD), write (WR), end of conversion (EOC),

and convert start (CONVST). Figures 6 and 7 and the

Timing Characteristics in the

Electrical Characteristics

table show the operation of the interface. DB0–DB3,

together with the output-only DB4–DB15, also output

the 16-bit conversion result. All bits are high imped-

ance when

RD = 1 or CS = 1.

R

VV

mA

S

FAULT MAX

=

−

_

7

20

MAX11047

MAX11048

MAX11049

CLAMP

S/H

16-BIT ADC

CLAMP

SOURCE

INPUT

SIGNAL

PIN

VOLTAGE

S/H

16-BIT ADC

REF

BUF

CONFIGURATION

REGISTERS

INTERFACE

AND

CONTROL

BANDGAP

REFERENCE

CH0

AVDD

AGNDs

AGND

CH7

DB15

DB0

DB3

DB4

EOC

SHDN

CONVST

CS

RD

WR

DGND

DVDD

RDC

REFIO

INT REF

EXT REF

Figure 1. Required Setup for Clamp Circuit

SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)

30

20

0

10

-10

-20

-20

-15

-10

-5

0

5

10

15

20

25

-25

-30

40

AT SOURCE

AT CH_ INPUT

Figure 2. Input Clamp Characteristics

SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)

6

4

2

0

-2

-4

8

-20

-15

-10

-5

10

15

20

25

-25

0

5

AT CH_ INPUT

AT SOURCE

Figure 3. Input Clamp Characteristics (Zoom In)