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DM9013 датащи(PDF) 28 Page - Davicom Semiconductor, Inc.

номер детали DM9013
подробное описание детали  10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface
PDF  75 Pages
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производитель  DAVICOM [Davicom Semiconductor, Inc.]
домашняя страница  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9013 датащи(HTML) 28 Page - Davicom Semiconductor, Inc.

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DM9013
3-port switch with Processor Interface
28
Preliminary datasheet
DM9013-15-DS-P03
April 9, 2009
6.38 VLAN Control Register (53H)
Bit
Name
Default
Description
7
TOS6
PE0,RW
Full ToS Using Enable
0: check most significant 3-bit only of TOS
1: check most significant 6-bit of TOS
6
RESERVED
0,RO
Reserved
5
UNICAST
PE0,RW
Unicast packet can across VLAN boundary
4
VIDFF
PE0,RW
Replace VIDFF
3
VID1
PE0,RW
Replace VID01
2
VID0
PE0,RW
Replace VID0
1
PRI
PE0,RW
Replace priority field in the tag
0
VLAN
PE0,RW
VLAN mode enable
0: port-base VLAN
1: 802.1Q base VLAN mode enable
6.39 Switch Status Register (54H)
Bit
Name
Default
Description
7
MEM_BIST
PH0,RO
Address Memory Test BIST Status
0: OK
1: Fail
6:0
RESERVED
0,RO
Reserved
6.40 Bandwidth LED Control Register (55H)
Bit
Name
Default
Description
7,6
RESERVED
PH0,RW
Reserved
5
P2_TX
PH1,RW
Port 2 transmit as event of bandwidth LED source
4
P2_RX
PH0,RW
Port 2 receive as event of bandwidth LED source
3
P1_TX
PH1,RW
Port 1 transmit as event of bandwidth LED source
2
P1_RX
PH0,RW
Port 1 receive as event of bandwidth LED source
1
P0_TX
PH1,RW
Port 0 transmit as event of bandwidth LED source
0
P0_RX
PH0,RW
Port 0 receive as event of bandwidth LED source
6.41 Per Port Control/Status Index Register (60H)
Bit
Name
Default
Description
7:5
reserved
PHS0,RW reserved
4:2
reserved
0,RO
reserved
1:0
INDEX
PHS0,RW Port index for register 61h~84h
Write the port number to this register before write/read register 61h~84h.
6.42 Per Port Control Data Register (61H)
Bit
Name
Default
Description
7
RESERVED
PE0,RW
Reserved
6
PARTI_EN
PE0,RW
Enable Partition Detection
5
NO_DIS_RX
PE0,RW
Not Discard RX Packets when Ingress Bandwidth Control



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