MCP1790-3002ESLASHEB datasheet(13/34 Pages) MICROCHIP

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DS22075A-page 13

MCP1790/MCP1791

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1 and Table 3-2.

3.1

Input Voltage Supply (VIN)

Connect the unregulated or regulated input voltage

source to VIN. If the input voltage source is located sev-

eral inches away from the regulator or the input source

is a battery, it is recommended that an input capacitor

is used. A typical input capacitance value of 1 µF to

10 µF should be sufficient for most applications. The

type of capacitor used can be ceramic, tantalum or alu-

minum electrolytic. The low ESR characteristics of the

ceramic will yield better noise and PSRR performance

at high-frequency.

3.2

Ground (GND)

Tie GND to the negative side of the output and the

negative side of the input capacitor. Only the regulator

bias current flows out of this pin; there is no high

current. The regulator output regulation is referenced to

this pin. Minimize voltage drops between this pin and

the negative side of the load.

3.3

Regulated Output Voltage (VOUT)

The VOUT pin is the regulated output voltage of the reg-

ulator. A minimum output capacitance of 1.0 µF tanta-

lum, 1.0 µF electrolytic, or 4.7 µF ceramic is required

for stability. The MCP1790 is stable with ceramic,

tantalum, and electrolytic capacitors. See

Section 4.7

“Output Capacitor” for output capacitor selection

guidance.

3.4

Shutdown (SHDN)

The SHDN pin is an active-low input signal that turns

the regulator output voltage on and off. When the

SHDN input is at a logic-high level, the regulator output

voltage is enabled. When the SHDN input is pulled to a

logic-low level, the regulator output voltage is disabled.

When the SHDN input is pulled low, the PWRGD output

signal also goes low and the regulator enters a low qui-

escent current shutdown state where the typical quies-

cent current is 10 µA. The SHDN pin is bonded to VIN

in the 3-pin versions of the regulator. See Table 4-1.

3.5

Power Good Output (PWRGD)

The PWRGD pin is an open-drain output signal that is

used to indicate when the regulator output voltage is

within 90% (typically) of its nominal regulation value.

The PWRGD threshold has a typical hysteresis value

of 2%. The typical PWRGD delay time due to VOUT

rising above 90% +3% (maximum hysteresis) is 30 µs.

The typical PWRGD delay time due to VOUT falling

below 90% is 235 µs. These delay times are internally

fixed.

3.6

Exposed Pad (EP)

The DDPAK package has an exposed tab on the pack-

age. A heat sink may be mounted to the tab to aid in the

removal of heat from the package during operation.

The exposed tab or pad of all of the available packages

is at the ground potential of the regulator.

TABLE 3-1:

MCP1790 PIN FUNCTION TABLE

Pin No.

SOT-223-3

Pin No.

DDPAK-3

Symbol

Function

VIN

Unregulated Supply Voltage

2,Tab

GND

Ground Terminal

VOUT

Regulated Output Voltage

TABLE 3-2:

MCP1791 PIN FUNCTION TABLE

Pin No.

SOT-223-5

Pin No.

DDPAK-5

Symbol

Function

SHDN

Shutdown Input

VIN

Unregulated Supply Voltage

GND

Ground Terminal

VOUT

Regulated Output Voltage

PWRGD

Power Good Open-Drain Output

Tab

—

Connected to Ground

—

N/C

no connection

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