DM562AP datasheet(12/48 Pages) DAVICOM

12 / 48 page

DM562AP

V.90 Integrated Data/ Fax/Voice/Speakerphone

Modem Device Single Chip with Memory Built in

DM6588A Pin Description-PCI Interface only

Pin No.

Pin Name

I/O

Description

POWEROFF

Power Off when high

121

INT#

PCI Interrupt Request

This signal will be asserted low when an interrupt condition as defined in

CR5 is set and the corresponding mask bit in CR7 is not set.

PCLK

PCI System Clock

This signal is the PCI bus clock that provides timing for all bus phases.

The frequency is 33MHz.

PME#

Power Management Event

The signal indicates that a power management event.

124-127,2-5

9-12,14-17

29-32,38-41

51-56,64,65

AD31-AD0

I/O

PCI Address & Data Bus

These are the multiplexed address and data signals.

DM6588A will decode each address on the bus and respond if it is the target

being addressed.

IDSEL

Initialization Device Select

For the accesses to the configuration address space, the device select

Decoding is done externally and is signaled via this pin. This signal is asserted

high during configuration read and write access.

C/BE3#

C/BE2#

C/BE1#

C/BE0#

PCI Bus Command/Byte Enable

During the address phase, these signals define the bus command or the type of

the bus transaction that will take place.

During the data phase, these pins indicate which byte lanes contain valid data.

C/BE0# applies to bit7~0 and C/BE3# applies to bit 31~24.

FRAME#

PCI Cycle Frame

This signal is driven low by the master to indicate the beginning and duration

of a bus transaction. It is de-asserted when the transaction is in its final phase.

IRDY#

PCI Initiator Ready

This signal is driven low when the master is ready to complete the current data

phase of the transaction. A data phase is completed on any clock both IRDY#

and TRDY# are sampled asserted.

TRDY#

I/O

PCI Target Ready

This signal is driven low when the target is ready to complete the current data

phase of the transaction. During a read, it indicates that the valid data is asserted

During write, it indicates that the target prepares to accept data.

DEVSEL#

I/O

PCI Device Select

DM6588A asserts the signal low when it recognizes its target address after

FRAME# is asserted.

STOP#

I/O

PCI Stop

This signal is asserted low by the target device to request the master device to

stop the current transaction.

PERR#

I/O

PCI Parity Error

DM6588A will assert this signal low to indicate a parity error on any incoming

data.

SERR#

PCI System Error

This signal is asserted low when an address parity is detected with PCICS bit31

enabled. The system error asserts two clock cycles after the address if an

address parity error is detected.

Final

Version: DM562AP-DS-F03

Nov. 09, 2007

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