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PCF2129A датащи(PDF) 39 Page - NXP Semiconductors |
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PCF2129A датащи(HTML) 39 Page - NXP Semiconductors |
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39 / 68 page ![]() PCF2129A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 13 January 2010 39 of 68 NXP Semiconductors PCF2129A Integrated RTC, TCXO and quartz crystal The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 1 ⁄ 64 seconds in duration. 8.12.2 INT pulse shortening If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately when it is serviced, i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 22. Instructions for clearing the bit MSF can be found in Section 8.10.5. 8.12.3 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD bit (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is possible for watchdog timer interrupts. In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt. Fig 21. INT example for SI and MI when TI_TP is logic 0 001aag072 58 seconds counter minutes counter INT when SI enable MSF when SI enable INT when only MI enabled MSF when only MI enabled 59 59 11 00 00 01 12 (1) Indicates normal duration of INT pulse. The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, i.e. when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0. Fig 22. Example of shortening the INT pulse by clearing the MSF flag 001aaf908 58 seconds counter MSF INT SCL instruction 59 CLEAR INSTRUCTION 8th clock (1) |
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