ST7576 datasheet(21/54 Pages) SITRONIX

21 / 54 page

ST7576

Ver 1.0

21/54

2007/01/29

2C Interface protocol

The ST7576 supports command, data write addressed slaves on the bus.

Before any data is transmitted on the I

2C Interface, the device, which should respond, is addressed first. Four 7-bit slave

addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7576. The least significant bit of the slave

address is set by connecting the input SA0 and SA1 to either logic 0 or logic 1 (VDD1).

The I

2C Interface protocol is illustrated in Fig.10.

The sequence is initiated with a START condition (S) from the I

2C Interface master, which is followed by the slave address.

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I

2C Interface transfer. After

acknowledgement, one or more command words follow which define the status of the addressed slaves.

A command word consists of a control byte, which defines Co and A0, and a data byte.

The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a

cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command

or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,

depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set

to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer

is automatically updated and the data is directed to the intended ST7576 device. If the A0 bit of the last control byte is set to

logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received

commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus

master issues a STOP condition (P). If no acknowledge is generated by the master after a byte, the driver stops

transferring data to the master.

Fig 8 System configuration

Fig 9 Acknowledgement on the I

2C Interface

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