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ST7576 датащи(PDF) 17 Page - Sitronix Technology Co., Ltd. |
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ST7576 датащи(HTML) 17 Page - Sitronix Technology Co., Ltd. |
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17 / 54 page ![]() ST7576 Ver 1.0 17/54 2007/01/29 Configuration Pins CP I Set Booster stages. (“L”=4X; “H”=5X) CP pin set the default value of booster stages after reset , and booster stage can be changed by software instruction 1 BR I Set LCD bias ratio. (“L”=1/7; “H”=1/9) BR pin set the default value of bias ratio after reset , and bias ratio can be changed by software instruction 1 TMX I Mirror X: SEG bi-direction selection TMX connect to VSS : normal direction (SEG0àSEG101) TMX connect to VDD : reverse direction (SEG101àSEG0) 1 TMY I Mirror Y: COM bi-direction selection TMY connect to VSS (TMY=0): normal direction TMY connect to VDD (TMY=1): reverse direction See Pad Center Coordinates at page 3~10. 1 Test Pin T0~T8 T Do NOT use. Reserved for testing. Must be floating 9 T11 T Do NOT use. Reserved for testing. Must be pull high 1 T12 T Do NOT use. Reserved for testing. Must be pull low 1 ST7576 I/O PIN ITO Resister Limitation PIN Name ITO Resister PS[2:0], OSC, CP, BR, T11, T12 No Limitation T0~T8, VRS, VDX2, TMX, TMY Floating VDD1, VDD2, VSS <100Ω V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VM <500Ω A0, /WR, /RD, CSB, D7…D0 <1KΩ RESB RESB<10KΩ |
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