ST2202A datasheet(21/75 Pages) SITRONIX

21 / 75 page

ST2202A

Ver 2.5

21/75

9/16/2008

1.. C

K G

The ST2202 has two oscillators OSC and OSCX for both

high and low frequency needed. When oscillator mode

selection pin, XMD, is inputted high level, the high

frequency oscillator OSC adopts only one external resistor

to generate a high frequency clock OSCK which is used by

almost every block in chip. OSC can also change to be a

resonator/crystal oscillator by input low level to XMD.

The low frequency oscillator OSCX needs a 32768Hz

crystal and one capacitor to generator a precise frequency

CLK32 for Base timer, Timer1 and the reference clock of

baud rate generator (BGR).

Other clocks are sourced from either OSCK or CLK32 and

are listed below:

System clock:

SYSCK

LCD controller clock:

LCDCK

PSG and PWM DAC clock: PSGCK

BGR output clock:

BGRCK

SPI transmission clock:

SPICK

SYSCK

The system clock can be switched between OSCK and

CLK32 by resetting or setting XSEL (SYS[7]). After XSEL is

set (or reset), warm-up cycles will be initiated at the same

time. The original clock is still connected until the end of

warm-up cycles. Clock being used can be reported by

reading XSEL back.

Note: Test XSEL to confirm SYSCK is switched

over successfully before turning down the

original clock.

There are two options for warm-up cycles: 16 / 256 cycles,

which are controlled by WSKP (SYS[3]). Usually 16 cycles

are enough for OSC and OSCX.

LCDCK

The LCD controller has one four-bit divider to generate

LCDCK directly from OSCK for pixel clock and other

operations. This divider is controlled by LCKR[3:0] and the

data mode selection bit LMOD(LCKR[4]). Refer to TABLE

11-3 for settings of LCDCK.

PSGCK

PSGCK is the clock used by PSG and PWM DAC. It is

sourced from OSCK to make sure of one right and high

enough base frequency and to keep it unchanged. Bits of

PSGC[6:4] control the options of PSGCK. Refer to TABLE

11-4 for these options.

BGRCK

The ST2202 equips a baud rate generator (BGR), which is

controlled by BGR control register BCTR, locked frequency

selection register BRS, and divider control register BDIV.

The BGR utilizes digital PLL technique to lock a high

frequency

HIGH

around OSCK/2. This high frequency is

further scaled down via an integer divider to a desired

frequency BGRCK. The BGR uses CLK32 as reference

clock for the modulation of OSCK. There are two

modulation modes which can be selected by BMOD

(BCTR[1]). The modulation strength is also controllable by

setting or resetting BSTR (BCTR[2]).

The relation between locked frequency and BRS can be

found in the following equation.

BRS

⋅

CLK

FHIGH

Equation9-1

OSCK and

HIGH

are close related. Value of

HIGH

limits

the frequency range of the OSCK applied, which is also the

locking range of BGR, and is given by the following

equation, where α is the modulation strength coefficient.

OSCK

HIGH

−

⋅

≤

⋅

Equation9-2

Although the locked frequency is limited to be around

OSCK, lower frequency can still be obtained by one 8-bit

integer divider, which is assigned by BDIV. Thus BGRCK

can be expressed by Equation9-3.

BDIV

HIGH

BGRCK =

Equation9-3

SPICK

The SPI block has one three-bit divider to generate SPICK

directly from OSCK for transmission and other operations.

This divider is controlled by SCKR[6:4]. Refer to TABLE

11-7 for settings of SPICK.

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