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LT6350

6350f

APPLICATIONS INFORMATION

BOARD LAYOUT AND BYPASS CAPACITORS/DC1538A

DEMOBOARD

For single-supply applications it is recommended that

a high quality X5R or X7R, 0.1μF bypass capacitor be

placed directly between the V+ and the V– pin; the V– pin

(including the Exposed Pad on the DD8 package) should be

tied directly to a low impedance ground plane with minimal

routing. For split power supplies, it is recommended that

additional high quality X5R or X7R, 0.1μF capacitors

be used to bypass pin V+ to ground and V– to ground,

again with minimal routing. Small geometry (e.g., 0603)

surface mount ceramic capacitors have a much higher

self-resonant frequency than do leaded capacitors, and

perform best with the LT6350.

The +IN2 pin should be bypassed to ground with a high

quality ceramic capacitor of at least 0.1μF, both to reduce

the noise bandwidth of the recommended DC offset balance

resistor and to prevent changes in the common mode

reference voltage from being converted into a differential

output signal.

Stray parasitic capacitance at the –IN1 pin should be kept

to a minimum to prevent degraded stability resulting in

excessive ringing or oscillations. Traces at –IN1 should be

kept as short as possible, and any ground plane should

be stripped from under the pin and pin traces.

Because the outputs operate differentially, load imped-

ances seen by both outputs (stray or intended) should

be as balanced and symmetric as possible. This will help

preserve the balanced operation that minimizes the gen-

eration of even-order harmonic distortion in the output

stage and maximizes the rejection of common mode

signals and noise.

The DC1538A demoboard has been designed for the

evaluation of the LT6350 following the above layout prac-

tices. Its schematic and component placement are shown

in Figures 9 and 10.

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