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33988 датащи(PDF) 13 Page - Freescale Semiconductor, Inc

номер детали 33988
подробное описание детали  Dual Intelligent High-current Self-protected Silicon High Side Switch (8.0m廓)
PDF  34 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33988 датащи(HTML) 13 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33988
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
fSPI
3.0
MHz
Required Low State Duration for RST(24)
tWRST
50
350
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(25)
tCS
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(25)
tENBL
5.0
μs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(25)
tLEAD
50
167
ns
Required High State Duration of SCLK (Required Setup Time)(25)
tWSCLKh
167
ns
Required Low State Duration of SCLK (Required Setup Time)(25)
tWSCLKl
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(25)
tLAG
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)(26)
tSI(SU)
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time)(26)
tSI(HOLD)
25
83
ns
SO Rise Time
CL = 200pF
tRSO
25
50
ns
SO Fall Time
CL = 200pF
tFSO
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time(26)
tRSI
50
ns
SI, CS, SCLK, Incoming Signal Fall Time(26)
tRSI
50
ns
Time from Falling Edge of CS to SO Low-impedance(27)
tSO(EN)
145
ns
Time from Rising Edge of CS to SO High-impedance(28)
tSO(DIS)
65
145
ns
Time from Rising Edge of SCLK to SO Data Valid(29)
0.2 x VDD ≤ SO ≤ 0.8 x VDD, CL = 200pF
tVALID
65
105
ns
Notes
24.
RST
low duration measured with outputs enabled and going to OFF or disabled condition.
25.
Maximum setup time required for the 33988 is the minimum guaranteed time needed from the microcontroller.
26.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27.
Time required for output status data to be available for use at SO. 1.0k
Ω on pull-up on CS.
28.
Time required for output status data to be terminated at SO. 1.0k
Ω on pull-up on CS.
29.
Time required to obtain valid data out from SO following the rise of SCLK.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5V
≤ VDD ≤ 5.5V, 6.0V ≤ VPWR ≤ 27V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit



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