Analog Integrated Circuit Device Data

Freescale Semiconductor

23

33988

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 11. Multiple 8-Bit Word SPI Communication

SERIAL INPUT COMMUNICATION

SPI communication is accomplished using 8-bit

messages. A message is transmitted by the MCU starting

with the MSB, D7, and ending with the LSB, D0 (Table 8).

Each incoming command message on the SI pin can be

interpreted using the following bit assignments: the MSB (D7)

is the watchdog bit and in some cases a register address bit

common to both outputs or specific to an output; the next

three bits, D6:D4, are used to select the command register;

and the remaining four bits, D3:D0, are used to configure and

control the outputs and their protection features.

Multiple messages can be transmitted in succession to

accommodate those applications where daisy chaining is

desirable, or to confirm transmitted data, as long as the

messages are all multiples of eight bits. Any attempt made to

latch in a message that is not eight bits will be ignored.

The 33988 has defined registers, which are used to

configure the device and to control the state of the output.

Table 9, summarizes the SI registers. The registers are

addressed via D6:D4 of the incoming SPI word (Table 8).

CS B

SI

SC L K

D7

D1 *

D2 *

D5 *

D6 *

D7 *

D0

D1

D6

D5

D2

D0 *

OD 5

OD 6

OD 7

D6

D7

OD 0

OD 1

OD 2

D1

D2

D5

F I G URE 4 b .

M U L T I P L E 8 b i t W O RD S P I C O M M UNI CA T I O N

NO T E S :

D0

SO

1.

R S T B i s i n a l o gi c 1 s t at e d u r i ng t h e a b o v e op er at i o n.

2 .

D 0 , D 1 , D 2 , . . ., a n d D 7 r e l a t e t o t h e m o s t r e c e n t o r d e r e d e n tr y o f d a ta i n to th e S P S S

3.

O D 0, O D 1, O D 2, . . . , an d O D 7 r e l a t e t o t h e f i r s t 8 b i t s o f o r de r e d f a u l t a n d s t a t u s da t a ou t o f t h e de v i c e .

4.

O D 0, O D 1, O D 2, . . . , a n d O D 7 r e pr e s en t t h e f i r s t 8 bi t s o f o r de r e d f a u l t a n d s t a t u s da t a ou t o f t h e S P S S

SCLK

SI

SO

RST

CS

2. D7:D0 relate to the most recent ordered entry of data into the device.

4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

Notes

3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

Table 8. SI Message Bit Assignment

Bit Sig SI Msg Bit

Message Bit Description

MSB

D7

Register address bit for output selection.

Also used for Watchdog: toggled to satisfy

watchdog requirements.

D6:D4

Register address bits.

D3:D1

Used to configure the inputs, outputs, and

the device protection features and SO status

content.

LSB

D0

Used to configure the inputs, outputs, and

the device protection features and SO status

content.

Table 9. Serial Input Address and Configuration Bit Map

SI

Register

Serial Input Data

D7 D6 D5 D4

D3

D2

D1

D0

STATR

s

0

0

0

0

SOA2

SOA1

SOA0

OCR

x

0

0

1

CSNS1

EN

IN1_SPI CSNS0

EN

IN0_SPI

SOCHLR s

0

1

0

SOCHs SOCL2s SOCL1s SOCL0s

CDTOLR s

0

1

1 OL_DIS

s

CD_DIS

s

OCLT1s OCLT0s

DICR

s

1

0

0

FAST

SR s

CSNS

high s

IN DIS s

A/Os

OSDR

0

1

0

1

0

OSD2

OSD1

OSD0

WDR

1

1

0

1

0

0

WD1

WD0

NAR

0

1

1

0

0

0

0

0

UOVR

1

1

1

0

0

0

UV_dis OV_dis

TEST

x

1

1

1

Freescale Internal Use (Test)

x = Don’t care.

s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =

HS1.