MAXQ3180-RAN+ datasheet(24/101 Pages) MAXIM

24 / 101 page

Low-Power, Multifunction, Polyphase AFE

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more bytes than are required by the current command,

the extra bytes are either ignored (if the MAXQ3180 is

busy processing the previous command) or are inter-

preted as the beginning of a new command. If the mas-

ter sends fewer bytes than are required by the current

command, the MAXQ3180 waits for SPI timeout, then

drops the transaction and resets the communication

channel. The duration of the timeout can be configured

through the COM_TIMO register.

Figures 5 and 6 show typical 2-byte reading and writing

transfers (without CRC byte).

Host Software Design

Individual message bytes sent through the SPI are

processed in a software routine contained in the ROM

firmware. For this reason, it is necessary to provide a

delay between successive bytes. This byte spacing

must be no less than 400 system clocks to ensure that

the MAXQ3180 has a chance to read and process the

byte before the arrival of the next one.

To read any virtual power registers, the host must first

confirm that the DSPRDY bit of the IRQ_FLAG register

is set, which indicates the last DSP cycle has complet-

ed, then proceed to reading all the desired virtual

power registers. For best communication efficiency, it is

recommended to complete reading the virtual power

registers before reading other registers. Virtual power

cycle time, from the moment the DSPRDY bit is set. Do

not forget to clear the DSPRDY bit, otherwise, host soft-

ware is not able to detect the completion of the new

DSP cycle. The MAXQ3180 does not clear the bit; it

only sets the bit whenever a DSP cycle processing is

completed. Users can clear the bit directly after the

confirmation that the bit is set. Clearing the DSPRDY bit

does not affect the DSP processing. It is strongly rec-

ommended that CRC be enabled for both read and

write to achieve reliable communications.

SSEL

SCLK

MOSI

MISO

READING DATA FROM MAXQ3180 THROUGH SPI INTERFACE

00 01

ADDRESS

DUMMY

0xC1

0xC2

NACK (0x4E)

DATA LSB

DATA MSB

ACK (0x41)

SSEL

SCLK

MOSI

MISO

10 01

ADDRESS

DUMMY

0xC1

0xC2

ACK (0x41)

NACK (0x4E)

ACK (0x41)

WRITING DATA TO MAXQ3180 THROUGH SPI INTERFACE

DATA LSB

DATA MSB

Figure 6. Write SPI Transfer

Figure 5. Read SPI Transfer

MAXQ3180-RAN+ датащи(PDF) 24 Page - Maxim Integrated Products

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