ATmega324PA datasheet(39/468 Pages) ATMEL

39 / 468 page

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

39 for details.

8.9

Timer/Counter Oscillator

ATmega164PA/324PA/644PA/1284P uses the same type of crystal oscillator for Low-frequency

Crystal Oscillator and Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page

35 for details on the oscillator and crystal requirements.

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-

nal clock source. See ”Clock Source Connections” on page 32 for details.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is

written to logic one. See ”The Output Compare Register B contains an 8-bit value that is contin-

uously compared with the counter value (TCNT2). A match can be used to generate an Output

Compare interrupt, or to generate a waveform output on the OC2B pin.” on page 159 for further

description on selecting external clock as input instead of a 32.768 kHz watch crystal.

8.10

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

8.11

System Clock Prescaler

The ATmega164PA/324PA/644PA/1284P has a system clock prescaler, and the system clock

can be divided by setting the ”CLKPR – Clock Prescale Register” on page 41. This feature can

be used to decrease the system clock frequency and the power consumption when the require-

ment for processing power is low. This can be used with all clock source options, and it will affect

the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clk-

FLASH are divided by a factor as shown in Table 8-16 on page 42.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

Table 8-15.

Start-up Times for the External Clock Selection

Power Conditions

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V

CC = 5.0V)

SUT1..0

BOD enabled

6 CK

14CK

Fast rising power

6 CK

14CK + 4.1 ms

Slowly rising power

6 CK

14CK + 65 ms

Reserved

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