ATmega324PA datasheet(91/468 Pages) ATMEL

91 / 468 page

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

• INT0/RXD1/PCINT26 – Port D, Bit 2

INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the

MCU.

RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is

enabled this pin is configured as an input regardless of the value of DDD2. When the USART

forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt

source.

• TXD0/PCINT25 – Port D, Bit 1

TXD0, Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD1.

PCINT25, Pin Change Interrupt Source 25: The PD1 pin can serve as an external interrupt

source.

• RXD0/PCINT24 – Port D, Bit 0

RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled

this pin is configured as an input regardless of the value of DDD0. When the USART forces this

pin to be an input, the pull-up can still be controlled by the PORTD0 bit.

PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt

source.

Table 13-13 on page 91 and Table 13-14 on page 92 relates the alternate functions of Port D to

the overriding signals shown in Figure 13-5 on page 80.

Table 13-13. Overriding Signals for Alternate Functions PD7:PD4

Signal Name

PD7/OC2A/

PCINT31

PD6/ICP1/

OC2B/

PCINT30

PD5/OC1A/

PCINT29

PD4/OC1B/XCK1/

PCINT28

PUOE

000

PUOV

000

DDOE

DDOV

PVOE

OC2A ENABLE

OC2B ENABLE

OC1A ENABLE

OC1B ENABLE

PVOV

OCA2A

OC2B

OC1A

OC1B

DIEOE

PCINT31 • PCIE3

PCINT30 • PCIE3

PCINT29 • PCIE3

PCINT28 • PCIE3

DIEOV

111

PCINT31 INPUT

ICP1 INPUT

PCINT30 INPUT

PCINT29 INPUT

PCINT28 INPUT

AIO

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