ATmega32HVB datasheet(235/273 Pages) ATMEL

235 / 273 page

235

8042A–AVR–07/09

ATmega16HVB/32HVB

32.13 2-wire Serial Interface Characteristics

Table 32-15 on page 235 describes the requirements for devices connected to the Two-wire

Serial Bus. The ATmega16HVB/32HVB Two-wire Serial Interface meets or exceeds these

requirements under the noted conditions.

Timing symbols refer to Figure 32-1 on page 236.

Notes:

1. In ATmega16HVB/32HVB, this parameter is characterized and not tested.

2. Cb = capacitance of one bus line in pF.

3. f

CK = CPU clock frequency

4. This requirement applies to all ATmega16HVB/32HVB Two-wire Serial Interface operation. Other devices connected to the

Two-wire Serial Bus need only obey the general fSCL requirement.

Table 32-15. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.8

VIH

Input High-voltage

2.1

5.5

(1)

Output Low-voltage

350 µA sink current

0.4

(1)

Rise Time for both SDA and SCL

300

tof

(1)

Output Fall Time from VIHmin to VILmax

Cb < 400 pF

(2)

250

tSP

(1)

Spikes Suppressed by Input Filter

Input Current each I/O Pin

0.1VBUS < Vi < 0.9VBUS

-5

µA

(1)

Capacitance for each I/O Pin

–

SCL

SCL Clock Frequency

(3) > max(16f

SCL, 450 kHz)

(4)

100

kHz

Value of Pull-up resistor

fSCL ≤ 100 kHz

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

tLOW

Low Period of the SCL Clock

fSCL ≤ 100 kHz

4.7

–

HIGH

High period of the SCL clock

SCL ≤ 100 kHz

4.0

–

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

HD;DAT

Data hold time

SCL ≤ 100 kHz

0.3

3.45

SU;DAT

Data setup time

SCL ≤ 100 kHz

250

–

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

tBUF

Bus free time between a STOP and START

condition

fSCL ≤ 100 kHz

4.7

–

BUS

0,4V

–

350µA

-------------------------------

BUS

0,4V

–

100µA

-------------------------------

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