ATmega32HVB datasheet(212/273 Pages) ATMEL

212 / 273 page

212

8042A–AVR–07/09

ATmega16HVB/32HVB

Figure 30-1. Serial Programming and Verify.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on OSCSEL Fuses, a valid clock must be present. The minimum low and high peri-

ods for the serial clock (SCK) input are defined as follows:

Low: > 2.2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2.2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

30.6.1

Serial Programming Algorithm

When writing serial data to the ATmega16HVB/32HVB, data is clocked on the rising edge of

SCK.

When reading data from the ATmega16HVB/32HVB, data is clocked on the falling edge of SCK.

See ”Serial Programming Characteristics” on page 237 for timing details.

To program and verify the ATmega16HVB/32HVB in the Serial Programming mode, the follow-

ing sequence is recommended (see four byte instruction formats in Table 30-12 on page 214):

Power-up sequence:

Apply power between V

CC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

Table 30-10. Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

SCK

PB5

Serial Clock

MOSI

PB6

Serial Data in

MISO

PB7

Serial Data out

VCC

GND

SCK

MISO

MOSI

RESET

+3.3 - 4.5V

VCC

GND

SCK

MISO

MOSI

RESET

+3.3 - 4.5V

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