ATmega32HVB datasheet(187/273 Pages) ATMEL

187 / 273 page

187

8042A–AVR–07/09

ATmega16HVB/32HVB

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.

27.10.6

TWAMR – TWI (Slave) Address Mask Register

• Bits 7:1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can

mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 27-23 shown the address match logic in

detail.

Figure 27-23. TWI Address Match Logic, Block Diagram

• Bit 0 – Res: Reserved Bit

This bit is an unused bit in the ATmega16HVB/32HVB, and will always read as zero.

27.10.7

TWBCSR – TWI Bus Control and Status Register

• Bit 7 - TWBCIF: TWI Bus Connect/Disconnect Interrupt Flag

Based on the TWBCIP bit, the TWBCIF bit is set when the TWI bus is connected or discon-

nected

(1). TWBCIF is cleared by hardware when executing the corresponding interrupt handling

vector. Alternatively, TWBCIF is cleared by writing a logic one to the flag. When the SREG I-bit,

TWBCIE (TWI Bus Connect/Disconnect Interrupt Enable), and TWBCIF are set, the TWI Bus

Connect/Disconnect Interrupt is executed. If both SDA and SCL are high during reset, TWBCIF

will be set after reset. Otherwise TWBCIF will be cleared after reset.

Note:

1. The TWEN bit in the TWCR register must be set for the Bus Connect/Disconnect feature to be

enabled.

Bit

654

(0xBD)

TWAM[6:0]

–TWAMR

Read/Write

R/W

Initial Value

Address

Match

Address Bit Comparator 0

Address Bit Comparator 6..1

TWAR0

TWAMR0

Address

Bit 0

Bit

543

(0xBE)

TWBCIF

TWBCIE

–

TWBDT1

TWBDT0

TWBCIP

TWBCSR

Read/Write

R/W

Initial Value

000

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