ATmega32HVB datasheet(181/273 Pages) ATMEL

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181

8042A–AVR–07/09

ATmega16HVB/32HVB

27.7.6

Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

The transfer must be initiated.

The EEPROM must be instructed what location should be read.

The reading must be performed.

The transfer must be finished.

Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct

the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The Master must keep control of the bus during all these steps, and the steps

should be carried out as an atomic operation. If this principle is violated in a multi-master sys-

tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the

master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 27-19. Combining Several TWI Modes to Access a Serial EEPROM

27.8

Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simultane-

ously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a slave receiver.

Table 27-6.

Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the Two-wire Serial

Bus and Two-wire Serial Inter-

face hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA

STO

TWINT

TWEA

0xF8

No relevant state information

available; TWINT = “0”

No TWDR action

No TWCR action

Wait or proceed current transfer

0x00

Bus error due to an illegal

START or STOP condition

No TWDR action

Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

Master Transmitter

Master Receiver

S = START

Rs = REPEATED START

P = STOP

Transmitted from master to slave

Transmitted from slave to master

SLA+W

ADDRESS

SLA+R

DATA

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