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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega325P датащи(PDF) 286 Page - ATMEL Corporation |
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ATmega325P датащи(HTML) 286 Page - ATMEL Corporation |
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286 / 364 page  286 8023F–AVR–07/09 ATmega325P/3250P Figure 25-10. Serial Programming and Verify (1) Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. V CC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz VCC GND XTAL1 SCK MISO MOSI RESET +1.8 - 5.5V AVCC +1.8 - 5.5V (2) |
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