ATmega325P datasheet(235/364 Pages) ATMEL

235 / 364 page

235

8023F–AVR–07/09

ATmega325P/3250P

23.5.3

Scanning the Clock Pins

The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-

tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and

Ceramic Resonator.

Figure 23-5 shows how each Oscillator with external connection is supported in the scan chain.

The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-

put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is

scanned in the same way. The output from the internal RC Oscillator is not scanned, as this

Oscillator does not have external connections.

Figure 23-5. Boundary-scan Cells for Oscillators and Clock Options

Table 23-2 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.

Notes:

1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between

the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is

preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock

configuration is considered fixed for a given application. The user is advised to scan the same

clock option as to be used in the final system. The enable signals are supported in the scan

chain because the system logic can disable clock options in sleep modes, thereby disconnect-

ing the Oscillator pins from the scan path if not provided.

Table 23-2.

Scan Signals for the Oscillator(1)(2)(3)

Enable Signal

Scanned Clock Line

Clock Option

Scanned Clock Line

when not Used

EXTCLKEN

EXTCLK (XTAL1)

External Clock

OSCON

OSCCK

External Crystal

External Ceramic Resonator

OSC32EN

OSC32CK

Low Freq. External Crystal

From

Cell

ClockDR

ShiftDR

Cell

To System Logic

FF1

From

Cell

ClockDR

UpdateDR

ShiftDR

Cell

EXTEST

From Digital Logic

XTAL1/TOSC1

XTAL2/TOSC2

Oscillator

ENABLE

OUTPUT

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