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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega325P датащи(PDF) 185 Page - ATMEL Corporation |
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ATmega325P датащи(HTML) 185 Page - ATMEL Corporation |
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185 / 364 page  185 8023F–AVR–07/09 ATmega325P/3250P • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Figure 18-10. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 01 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity Figure 18-11. USBSn Bit Settings USBSn Stop Bit(s) 01-bit 12-bit Figure 18-12. UCSZ Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 100 Reserved 101 Reserved 110 Reserved 1 1 1 9-bit |
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