ATmega325P datasheet(102/364 Pages) ATMEL

102 / 364 page

102

8023F–AVR–07/09

ATmega325P/3250P

14.10 Register Description

14.10.1

TCCR0A – Timer/Counter Control Register A

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written

when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-

pare match is forced on the Waveform Generation unit. The OC0A output is changed according

to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is

the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 14-2 and ”Modes of Operation”

on page 94.

Note:

1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM0A1:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

Bit

210

0x24 (0x44)

FOC0A

WGM00

COM0A1

COM0A0

WGM01

CS02

CS01

CS00

TCCR0A

Read/Write

R/W

Initial Value

Table 14-2.

Waveform Generation Mode Bit Description

(1)

Mode

WGM01

(CTC0)

WGM00

(PWM0)

Timer/Counter Mode

of Operation

TOP

Update of

OCR0A at

TOV0 Flag Set

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR0A

Immediate

MAX

Fast PWM

0xFF

BOTTOM

MAX

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