M16CSLASH56D datasheet(63/85 Pages) RENESAS

63 / 85 page

REJ03B0307-0110 Rev.1.10 Dec 01, 2009

Page 63 of 83

M16C/5LD Group, M16C/56D Group

5. Electrical Characteristics

5.1.4

Flash Memory Electrical Characteristics

Notes:

Set the PM17 bit in the PM1 register to 1 (one wait).

When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in

the PM1 register to 1 (one wait)

Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub

clock as the CPU clock source, a wait is not necessary.

Notes:

Definition of program and erase cycles:

The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000),

each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to

a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once

without erasing the block (rewrite prohibited).

Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to

retain data on the erasure cycles of each block and limit the number of erase operations to a certain number.

If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

The data hold time includes time that the power supply is off or the clock is not supplied.

After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase

sequence cannot be completed.

Table 5.5

CPU Clock When Operating Flash Memory (f(BCLK))

VCC = 2.7 to 5.5 V, at Topr = -40 to 85°C unless otherwise specified.

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

CPU rewrite mode

10 (1)

MHz

f(SLOW_R)

Slow read mode

5 (3)

MHz

Low current consumption read mode

fC(32.768)

kHz

Data flash read

2.7 V < VCC ≤ 3.0 V

16 (2)

MHz

3.0 V < VCC ≤ 5.5 V

20 (2)

Table 5.6

Flash Memory (Program ROM 1, 2) Electrical Characteristics

VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

Program and erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C

1,000 (2)

times

Two words program time

VCC = 3.3 V, Topr = 25°C

150

4000

μs

Lock bit program time

VCC = 3.3 V, Topr = 25°C

3000

μs

Block erase time

VCC = 3.3 V, Topr = 25°C

0.2

3.0

td(SR-SUS)

Time delay from suspend request

until suspend

5 + CPU clock

× 3 cycles

Interval from erase start/restart

until following suspend request

μs

Suspend interval necessary for

auto-erasure to complete (7)

Time from suspend until erase

restart

30 + CPU

clock × 1 cycle

μs

Program, erase voltage

2.7

5.5

Read voltage

Topr= -40 to 85

°C2.7

5.5

Program, erase temperature

°C

tPS

Flash Memory Circuit Stabilization Wait Time

μs

Data hold time (6)

Ambient temperature = 55

°C

year

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