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AT34C02C датащи(PDF) 5 Page - ATMEL Corporation |
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AT34C02C датащи(HTML) 5 Page - ATMEL Corporation |
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5 / 18 page ![]() 5 5242B–SEEPR–01/09 AT34C02C STANDBY MODE: The AT34C02C features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps (a) Create a start bit condition, (b) Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. SCL SDA 12 38 9 Start Bit Start Bit Stop Bit Dummy Clock Cycles t wr (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT SCL SDA |
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