ATmega165 datasheet(187/336 Pages) ATMEL

187 / 336 page

187

ATmega165/V

2573G–AVR–07/09

consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-

ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the

Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the

Analog Comparator. See “Internal Voltage Reference” on page 42.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode

defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if

the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-

log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to

be triggered by the Analog Comparator. The comparator output is in this case directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

written logic zero, no connection between the Analog Comparator and the Input Capture

function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator inter-

rupt. The different settings are shown in Table 78.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Table 78. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

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