ATmega165 datasheet(166/336 Pages) ATMEL

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ATmega165/V

2573G–AVR–07/09

USART Register

Description

USART I/O Data Register –

UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buffer Register (TXB) will be the destination for data written to the UDR Register

location. Reading the UDR Register location will return the contents of the Receive Data

Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is

set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART

Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,

the Transmitter will load the data into the Transmit Shift Register when the Shift Register

is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever

the receive buffer is accessed. Due to this behavior of the receive buffer, do not use

Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the

receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-

abled, the receive buffer will be flushed and consequently the RXC bit will become zero.

The RXC Flag can be used to generate a Receive Complete interrupt (see description of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit buffer (UDR). The TXC

Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit

Complete interrupt (see description of the TXCIE bit).

Bit

RXB[7:0]

UDR (Read)

TXB[7:0]

UDR (Write)

Read/Write

R/W

Initial Value

Bit

7654

321

RXC

TXC

UDRE

DOR

UPE

U2X

MPCM

UCSRA

Read/Write

R/W

Initial Value

0010

000

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