ATmega165 datasheet(110/336 Pages) ATMEL

110 / 336 page

110

ATmega165/V

2573G–AVR–07/09

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the

OCR1x Registers are updated with the double buffer value (at BOTTOM). When either

OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when

TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNT1 and the OCR1x.

As Figure 48 shows the output generated is, in contrast to the phase correct mode, sym-

metrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COM1x1:0 to three (See Table on page 114). The actual OC1x value will only be visible

on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The

PWM waveform is generated by setting (or clearing) the OC1x Register at the compare

match between OCR1x and TCNT1 when the counter increments, and clearing (or set-

ting) the OC1x Register at compare match between OCR1x and TCNT1 when the

counter decrements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase and frequency correct PWM mode. If the OCR1x

is set equal to BOTTOM the output will be continuously low and if set equal to TOP the

output will be set to high for non-inverted PWM mode. For inverted PWM the output will

have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 =

9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

fOCnxPFCPWM

clk_I/O

NTOP

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