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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega128 датащи(PDF) 168 Page - ATMEL Corporation |
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ATmega128 датащи(HTML) 168 Page - ATMEL Corporation |
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168 / 386 page  168 2467S–AVR–07/09 ATmega128 and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summa- rized below: • Bit 2 – CPHA: Clock Phase The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example. The CPHA func- tionality is summarized below: • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f osc is shown in the following table: Table 70. CPOL functionality CPOL Leading edge Trailing edge 0 Rising Falling 1 Falling Rising Table 71. CPHA functionality CPHA Leading edge Trailing edge 0 Sample Setup 1Setup Sample Table 72. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency 00 0 f osc /4 00 1 f osc /16 01 0 f osc /64 01 1 f osc /128 10 0 f osc /2 10 1 f osc /8 11 0 f osc /32 11 1 f osc /64 |
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