ATmega128 datasheet(152/386 Pages) ATMEL

152 / 386 page

152

2467S–AVR–07/09

ATmega128

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the output compare (OC2) is cleared on the compare

match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the

output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 66. The TCNT2 value is in the timing diagram shown as a histo-

gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2 and TCNT2.

Figure 66. Fast PWM Mode, Timing Diagram

The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-

ting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM21:0 to 3 (see Table 66 on page 158). The actual OC2 value

will only be visible on the port pin if the data direction for the port pin is set as output. The PWM

waveform is generated by setting (or clearing) the OC2 Register at the compare match between

OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the coun-

ter is cleared (changes from MAX to BOTTOM).

TCNTn

OCRn Update

and

TOVn Interrupt Flag Set

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

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