ATmega128 datasheet(148/386 Pages) ATMEL

148 / 386 page

148

2467S–AVR–07/09

ATmega128

bottom

Signalize that TCNT2 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

T2). clkT2 can be generated from an external or internal clock source,

selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk

T2 is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR2). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the output compare output

OC2. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 150.

The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by

the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

Output Compare

Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the

output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global inter-

rupt flag in SREG is set), the output compare flag generates an output compare interrupt. The

OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag

can be cleared by software by writing a logical one to its I/O bit location. The waveform genera-

tor uses the match signal to generate an output according to operating mode set by the

WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used

by the waveform generator for handling the special cases of the extreme values in some modes

of operation (see “Modes of Operation” on page 150). Figure 63 shows a block diagram of the

output compare unit.

Figure 63. Output Compare Unit, Block Diagram

The OCR2 Register is double buffered when using any of the pulse width modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

ATmega128 датащи(PDF) 148 Page - ATMEL Corporation

ATmega128 датащи(HTML) 148 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL