ATmega128 datasheet(154/386 Pages) ATMEL

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154

2467S–AVR–07/09

ATmega128

Figure 67. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-

put can be generated by setting the COM21:0 to 3 (see Table 67 on page 158). The actual OC2

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC2 Register at the compare match

between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2

PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of Period 2 in Figure 67 OCn has a transition from high to low even though there

is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.

There are two cases that give a transition without a Compare Match:

•

OCR2A changes its value from MAX, like in Figure 67. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

fOCnPCPWM

clk_I/O

N 510

⋅

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