ATmega128 datasheet(147/386 Pages) ATMEL

147 / 386 page

147

2467S–AVR–07/09

ATmega128

The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the waveform generator to generate

a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare

Unit” on page 148. for details. The compare match event will also set the compare flag (OCF2)

which can be used to generate an output compare interrupt request.

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2

counter value and so on).

The definitions in Table 63 are also used extensively throughout the document.

Timer/Counter

Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the clock select logic which is controlled by the clock select (CS22:0) bits located

in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see

“Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 144.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

62 shows a block diagram of the counter and its surroundings.

Figure 62. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT2 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T0 in the following.

top

Signalize that TCNT2 has reached maximum value.

Table 63. Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The

assignment is dependent on the mode of operation.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

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