ATmega162 datasheet(154/324 Pages) ATMEL

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154

2513K–AVR–07/09

ATmega162/V

cycles, it executes the interrupt routine, and resumes execution from the instruction

following SLEEP.

•

Reading of the TCNT2 Register shortly after wake-up from Power-save may give an

incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2

must be done through a register synchronized to the internal I/O clock domain.

Synchronization takes place for every rising TOSC1 edge. When waking up from Power-

save mode, and the I/O clock (clk

I/O) again becomes active, TCNT2 will read as the previous

value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC

clock after waking up from Power-save mode is essentially unpredictable, as it depends on

the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:

Write any value to either of the registers OCR2 or TCCR2.

Wait for the corresponding Update Busy Flag to be cleared.

Read TCNT2.

•

During asynchronous operation, the synchronization of the Interrupt Flags for the

Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is

therefore advanced by at least one before the processor can read the Timer value causing

the setting of the Interrupt Flag. The output compare pin is changed on the Timer clock and

is not synchronized to the processor clock.

Timer/Counter

Interrupt Mask

• Bit 4 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 2 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

Bit

432

TOIE1

OCIE1A

OCIE1B

OCIE2

TICIE1

TOIE2

TOIE0

OCIE0

TIMSK

Read/Write

R/W

Initial Value

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