ATmega162 datasheet(150/324 Pages) ATMEL

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2513K–AVR–07/09

ATmega162/V

• Bit 5:4 – COM21:0: Compare Match Output Mode

These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits

are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.

However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set

in order to enable the output driver.

When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0

bit setting. Table 61 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a

normal or CTC mode (non-PWM).

Table 62 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare

Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 145 for

more details.

Table 63 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct

PWM mode.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare

Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

146 for more details.

Table 61. Compare Output Mode, non-PWM Mode

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Toggle OC2 on Compare Match.

Clear OC2 on Compare Match.

Set OC2 on Compare Match.

Table 62. Compare Output Mode, Fast PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on Compare Match, set OC2 at TOP.

Set OC2 on Compare Match, clear OC2 at TOP.

Table 63. Compare Output Mode, Phase Correct PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on Compare Match when up-counting. Set OC2 on Compare

Match when down-counting.

Set OC2 on Compare Match when up-counting. Clear OC2 on Compare

Match when down-counting.

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