ATmega162 datasheet(103/324 Pages) ATMEL

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103

2513K–AVR–07/09

ATmega162/V

• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

Note:

In ATmega161 OCIE2 and TOIE2 have switched places in the TIMSK register.

Timer/Counter

Interrupt Flag Register

– TIFR

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In

phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at

0x00.

• Bit 0 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the

data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and

OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.

Note:

In ATmega161 OCF2 and TOV2 have switched places in the TIFR register.

Bit

765

4321

TOV1

OCF1A

OCF1B

OCF2

ICF1

TOV2

TOV0

OCF0

TIFR

Read/Write

R/W

Initial Value

000

0000

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