ATmega16 datasheet(210/357 Pages) ATMEL

210 / 357 page

210

2466S–AVR–05/09

ATmega16(L)

single conversions, and the first free running conversion) when CK

ADC2 is low will take the same

amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled

clock cycle). A conversion initiated by the user when CK

ADC2 is high will take 14 ADC clock

cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initi-

ated immediately after the previous conversion completes, and since CK

ADC2 is high at this time,

all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock

cycles.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may

be subjected to non-linear amplification. An external low-pass filter should be used if the input

signal contains higher frequency components than the gain stage bandwidth. Note that the ADC

clock frequency is independent of the gain stage bandwidth limitation. For example, the ADC

clock period may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the band-

width of this channel.

If differential gain channels are used and conversions are started by Auto Triggering, the ADC

must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is

reset before the conversion is started. Since the gain stage is dependent of a stable ADC clock

prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the

ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended con-

versions are performed. The result from the extended conversions will be valid. See “Prescaling

and Conversion Timing” on page 207 for timing details.

Changing Channel

or Reference

Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

When ADATE or ADEN is cleared.

During conversion, minimum one ADC clock cycle after the trigger event.

After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

Special care should be taken when changing differential channels. Once a differential channel

has been selected, the gain stage may take as much as 125 µs to stabilize to the new value.

Thus conversions should not be started within the first 125 µs after selecting a new differential

channel. Alternatively, conversion results obtained within this period should be discarded.

The same settling time should be observed for the first differential conversion after changing

ADC reference (by changing the REFS1:0 bits in ADMUX).

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