ATmega16 datasheet(157/357 Pages) ATMEL

157 / 357 page

157

2466S–AVR–05/09

ATmega16(L)

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will

no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be

flushed when the receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive

Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is

cleared. The following code example shows how to flush the receive buffer.

Note:

1. See “About Code Examples” on page 7.

Asynchronous

Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver.

The asynchronous reception operational range depends on the accuracy of the internal baud

rate clock, the rate of the incoming frames, and the frame size in number of bits.

Asynchronous Clock

Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 73

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and 8 times the baud rate for Double Speed mode. The horizon-

tal arrows illustrate the synchronization variation due to the sampling process. Note the larger

time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero

are samples done when the RxD line is idle (i.e., no communication activity).

Figure 73. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

Assembly Code Example

(1)

USART_Flush:

sbis

UCSRA, RXC

ret

r16, UDR

rjmp

USART_Flush

C Code Example(1)

void

USART_Flush( void )

{

unsigned char

dummy;

while

( UCSRA & (1<<RXC) ) dummy = UDR;

}

START

IDLE

BIT 0

123

678

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

ATmega16 датащи(PDF) 157 Page - ATMEL Corporation

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